Altering bit sequences to contain predetermined patterns

Details Altering bit sequences to contain predetermined patterns Altering bit sequences to contain predetermined patterns

1998-05-08

2000-05-09

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

364717, G01R 3128, G06F 1100

Patent

active

060618183

ABSTRACT:
A low-overhead scheme for built-in self-test of digital designs incorporating scan allows for complete (100%) fault coverage without modifying the function logic and without degrading system performance (beyond using scan). By altering a pseudo-random bit sequence with bit-fixing logic at an LFSR's serial output, deterministic test cubes that detect random pattern-resistant faults are generated. A procedure for synthesizing the bit-fixing logic allows for complete fault coverage with low hardware overhead. Also, the present approach permits the use of small LFSR's for generating the pseudo-random bit sequence. The faults that are not detected because of linear dependencies in the LFSR can be detected by generating more deterministic cubes at the expense of additional bit-fixing logic.

REFERENCES:
patent: 4503537 (1985-03-01), McAnney
patent: 4961159 (1990-10-01), McLeod et al.
patent: 5485471 (1996-01-01), Bershteyn
patent: 5612963 (1997-03-01), Koenemann et al.
patent: 5774477 (1998-06-01), Ke

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