Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-09-29
2002-10-08
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S729000, C716S030000
Reexamination Certificate
active
06463561
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method and system for detecting faults in electronic circuits by employing an almost full-scan method in which selected flip-flops are removed from the scan chains in order to improve overall performance.
2. Description of Related Art
The test application techniques used by most scan-based BIST architectures can be broadly characterized into two categories: test-per-clock and test-per-scan. In test-per-clock BIST, a test vector is applied and its response is captured in every clock cycle. FIG.
1
(
a
) shows a simple test-per-clock configuration using an LFSR as a pattern generator and a MISR as a response compactor. Test patterns can also be applied using an LFSR and an idler register as shown in FIG.
1
(
b
). The feature of this architecture is that all outputs (primary outputs or observation points) are connected to the MISR in parallel so that the responses are compressed in every clock cycle. This leads to shorter test application time. If the Circuit Under Test (CUT) is a sequential circuit, internal flip-flops can be configured as scan chains to improve the controllability or as a part of the MISR to increase the observability. However, configuring flip-flops as internal scan chains does not have the capability to observe the internal signals as regular scan flip-flops do. This is because if they are also used to capture the response, there is no time allowed for the response to be shifted out. That is, the response captured in one clock cycle may be corrupted by the responses of the subsequent clock cycles. Thus, to gain the observability from the internal scan chains, they must also be configured as a part of the MISR and consequently an XOR structure is necessary at every output of the scan flip-flop. This leads to a higher area overhead. In general, a large MISR is required for the test-per-clock BIST. Some of the popular test-per-clock BIST structures are BILBO based designs, and the circular self-test or circular BIST techniques. The primary advantage of these test-per-clock schemes is the relatively shorter test application time needed for achieving a desired fault coverage. The disadvantages are its high area overhead and performance degradation.
FIG.
2
(
a
) shows a basic test-per-scan BIST configuration. The internal (or external) scan chain is used to apply test vectors as well as capture the responses. First, the test vector is applied after shifting in the vector by clocking the serial scan chains for l cycles, where l is the length of the longest scan chain. Next, the response is captured into the scan chains by clocking the scan flip-flops in the capture mode once. The response is then shifted out to a MISR while the next vector is shifted in. A typical test-per-scan BIST structure is the STUMPS architecture as shown in FIG.
2
(
b
). STUMPS uses multiple parallel scan chains to apply test patterns and capture the responses. Test-per-scan architectures primarily require lower overheads (both area and performance), however the test application time increases as the length of the scan chain increases.
Useful discussions concerning the state of the art are disclosed in the following two (2) U.S. Patents, both assigned to AT&T Corp., Murray Hill, N.J. U.S. Pat. No. 5,329,533 entitled “Partial-Scan Built-in Self-Test Technique” and U.S. Pat. No. 5,450,414 entitled “Partial-Scan Built-In Self-Testing Circuit Having Improved Testability” both naming Chih-Jen Lin, Laurenceville, N.J. as the inventor.
Recently, a scan-based BIST scheme has been incorporated into pseudo-random BIST (called PSBIST). The BIST capability is built on top of a full-scan or partial-scan circuit by adding a test pattern generator, an output data compactor and a BIST controller.
FIG. 3
shows the schematic of the PSBIST which is very similar to the STUMPS. The network N can be either a combinational circuit (full-scan) or a sequential circuit (partial-scan) with no cycles through flip-flops of size greater than one (called Near Acyclic Circuit or NAC). The test pattern generator consists of an LFSR and a phase shifter (PS). The output responses are passed through a space compactor (SC) which feeds to a MISR. Optional test points can be added to increase the fault coverage. The test application strategy of PSBIST combines both test-per-clock and test-per-scan methodologies. The circuit responses at the primary outputs are compressed by the MISR in every clock cycle similar to the test-per-clock scheme. The responses are also captured into the scan chains in every scan cycle (l+1 clock cycles, where l is the length of the longest scan chain) and then compressed by the MISR when the responses are shifted out as typical test-per-scan testing scheme does. By doing so, the desired fault coverage can be reached much earlier than the conventional test-per-scan approach with similar overheads.
SUMMARY OF THE INVENTION
It has been observed that under PSBIST with above mentioned test application strategy, scanning all flip-flops may not result in a version with the highest fault coverage under a practical limit on the length of the random sequence. Removing some flip-flops from the scan chains which have reasonable controllabilities and relatively high observabilities through the network's primary outputs may actually improve the fault coverage and significantly reduce the test application time. An example is given in Section A to illustrate this point.
Based on this observation, in Section B a strategy is proposed for identifying flip-flops to be removed from the scan chains for improving the network's random pattern testability under PSBIST architecture. The technique starts with a full-scan circuit and iteratively identifies flip-flops to be removed from the scan chains to increase the observability of the circuit so that faults activated during the scan cycles can be observed at the primary output. The influence of the circuit random testability due to un-scanning a flip-flop is captured by a cost function. Note that the objective of un-scanning flip-flops is not for area minimization—it's only for maximizing the random pattern testability. For most of circuits, only a small number of flip-flops will be un-scanned and thus the resulting circuits are almost full-scan circuits.
In Section C, experimental result s are presented to illustrate that the proposed methodology produces an almost full-scan circuit with a higher fault coverage and shorter test application time than its full-scan counterpart.
REFERENCES:
patent: 5329533 (1994-07-01), Lin
patent: 5450414 (1995-09-01), Lin
patent: 5659717 (1997-08-01), Tse et al.
patent: 6070261 (2000-05-01), Tamarapalli
patent: 6330696 (2001-12-01), Zorian et al.
Bhawmik Sudipta
Cheng Kwang-Ting
Tsai Huan-Chih
Mendelsohn & Associates, P.C.
Moise Emmanuel L.
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