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Multi-layer cyclic redundancy check code in wireless...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-layer cyclic redundancy check code in wireless...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-level cell memory device and method thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-level error detection and correction technique for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-level file representation corruption

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Multi-level signal memory with LDPC and interleaving

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-mode decoding for digital audio broadcasting and other...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-mode hybrid ARQ scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-mode hybrid ARQ scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-mode programmable scan flop

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Multi-mode Reed-Solomon decoder based upon the PGZ algorithm...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-phase clock generation circuit and clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Multi-phase test point insertion for built-in self test of integ

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Multi-port memory device having serial I/O interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Multi-port memory testing method utilizing a sequence...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Multi-port scan chain register apparatus and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Multi-protocol monitor

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Multi-purpose BER tester (MPBERT) for very high RZ and NRZ...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Multi-rate codec with puncture control

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Multi-rate reed-solomon encoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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