Multi-port memory device having serial I/O interface

Details Multi-port memory device having serial I/O interface Multi-port memory device having serial I/O interface

2006-08-08

2006-08-08

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S733000

Reexamination Certificate

active

07089465

ABSTRACT:
The multi-port memory device includes a plurality of ports supporting serial I/O interface, and the plurality of ports includes a transmission pad and a reception pad. The multi-port memory device includes: a memory core; a control block for generating an internal command signal, an internal address and a control signal, which correspond to the command and are necessary for an operation of the memory core, using commands and addresses inputted to the plurality of ports packet form; and a mode selection block for combining signals applied to plurality of mode selection pads and generating a test mode flag signal, in which I/O data assigned to the transmission pad and the reception pad in a test mode in response to the test mode flag signal are exchanged with the memory core through the ports.

REFERENCES:
patent: 4982360 (1991-01-01), Johnson et al.
patent: 5910181 (1999-06-01), Hatakenaka et al.
patent: 6661735 (2003-12-01), Lee
patent: 6771558 (2004-08-01), Kim
patent: 6996027 (2006-02-01), Shin
patent: 7006402 (2006-02-01), Park et al.

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