Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-10-03
2006-10-03
Britt, Cynthia (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
07117409
ABSTRACT:
In a method of testing a multi-port memory in accordance with a test pattern, test clock signals having the same test clock frequency but with different delay periods introduced therein are generated for controlling memory access through the different access ports of the memory. Consecutive memory operations of a test element of the test pattern are then conducted in a folded sequence upon a memory cell through the different access ports in accordance with the test clock signals such that the memory operations are completed within the same test clock cycle of the test element.
REFERENCES:
patent: 6216241 (2001-04-01), Fenstermaker et al.
patent: 6510530 (2003-01-01), Wu et al.
patent: 6563751 (2003-05-01), Wu
patent: 10302475 (1998-11-01), None
patent: 11096765 (1999-04-01), None
“Realistic Fault Models and Test Procedure for Multi-port SRAMs” by Hamdioui et al.□□IEEE International Workshop on Memory Technology, Design and Testing, Publication Date: 2001 On pp. 65-72 INSPEC Accession No. 7137971.
“A Built-in Self-testing Method for Embedded Multiport Memory Arrays” by Narayanan et al. Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference Publication Date: May 18-20, 2004 vol. 3, On pp. 2027-2032.
Chi-Feng Wu, et al., “Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories,” Proceedings of the 38th Design Automation Conference, DAC 2001, Jun. 18-22, 2001, Las Vegas, NV, USA.
Cheng Kao-Liang
Huang Chih-Tsun
Wang Chih-Wea
Wu Cheng-Wen
Britt Cynthia
Ladas & Parry LLP
National Tsing Hua University
LandOfFree
Multi-port memory testing method utilizing a sequence... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Multi-port memory testing method utilizing a sequence..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-port memory testing method utilizing a sequence... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3658050