Multi-phase clock generation circuit and clock...

Details Multi-phase clock generation circuit and clock... Multi-phase clock generation circuit and clock...

2006-07-04

2006-07-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C327S002000

Reexamination Certificate

active

07073098

ABSTRACT:
A circuit is provided to prevent improper locking of a DLL circuit without providing any limitation to the reference clock frequency. By detecting the time difference between edges of multi-phase clocks Ck1–Ck6,a delay time detection signal DT1corresponding to a delay time 5τ from the multi-phase clock Ck1to the multi-phase clock Ck6is generated. An Up1signal is forcibly output to a charge pump circuit CP1based on this delay time detection signal DT1,and the output of a Down1 signal is suppressed.

REFERENCES:
patent: 5663665 (1997-09-01), Wang et al.
patent: 6329854 (2001-12-01), Lee et al.
patent: 6414526 (2002-07-01), Guinea et al.
patent: 6556488 (2003-04-01), Han
patent: 6628154 (2003-09-01), Fiscus
patent: 2002/0041196 (2002-04-01), Demone et al.
patent: 2003/0141910 (2003-07-01), Reindl
patent: 2004/0000937 (2004-01-01), Byun et al.
patent: 2000 022524 (2000-02-01), None
patent: 2000 224029 (2000-08-01), None

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