Concatenation of turbo-TCM with space-block coding

Concealing errors in transport stream data

Concentrated parity technique for handling double failures...

Concurrent generation of ECC error syndromes and CRC validation

Concurrent memory control for turbo decoders

Concurrent production of CRC syndromes for different data...

Concurrent row/column syndrome generator for a product code

Configurable architecture and its implementation of viterbi...

Configurable decoder and method for decoding a reed-solomon...

Configurable encoder and method for generating a...

Configurable error detection and correction engine that has...

Configurable interface module

Configurable Reed-Solomon controller and method

Configurable, fast, 32-bit CRC generator for 1-byte to...

Connecting multiple test access port controllers on a single...

Construction of an optimized SEC-DED code and logic for soft...

Construction of irregular LDPC (low density parity check)...

Content addressable memory having reduced power consumption

Content addressable memory with error signaling

Content and channel aware object scheduling and error control