Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-05-11
2002-03-05
Baker, Stephen M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S784000
Reexamination Certificate
active
06353909
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
TECHNICAL FIELD
The present invention is generally related to data communications and, more particularly, is related to a Reed-Solomon (“RS”) encoder and method for minimizing or eliminating errors in data communication.
BACKGROUND OF THE INVENTION
Communication of information in the form of digital data is quite commonplace in today's society. There are many different communications channels that may be employed to facilitate such data communication. Such channels may include existing telecommunications networks, the air, optical fiber networks, or other like media. It is often the case that the communications channels chosen do not provide a perfect medium to transfer data information, and for various reasons such as noise, interference, or other phenomena, errors may be introduced into the data stream transmitted across a particular channel.
Many different approaches have been proposed to either reduce or eliminate errors in data communications. One such approach is to employ Reed-Solomon encoding. When employing Reed-Solomon encoding, data is transmitted in codewords which include a number of parity symbols along with the original data symbols. The parity symbols are generated using a Reed-Solomon encoder. These parity symbols may be employed to correct errors in a received data signal.
When using Reed-Solomon encoding, a number 2t of parity symbols may be generated to allow a data system to correct up to t possible errors in the transmitted data. However, for each different number of total parity symbols generated, there is a unique Reed-Solomon generator polynomial with a specific number of coefficients employed. Thus, the typical Reed-Solomon encoder creates a specific number of parity symbols, which limits its usefulness if more or less parity symbols are desired.
SUMMARY OF THE INVENTION
The present invention provides a configurable Reed-Solomon encoder and method that addresses the above concerns. In one embodiment, the configurable Reed-Solomon encoder comprises a distributed multiply accumulator, a parallel latch bank operatively coupled to the distributed multiply accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the distributed multiply accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.
The present invention can also be viewed as providing a method for generating a Reed-Solomon codeword. Broadly stated, the method comprises the steps of: generating a parity symbol output with a multiply accumulator, distributing the operation of the multiply accumulator among a number of parallel latches, and generating a data output from a data input and a number of parity symbols stored in the parallel latches.
A significant advantage of the present invention is that it is highly configurable to implement Reed-Solomon encoding for different data communications protocols, etc. Specifically, the Reed-Solomon encoder of the present invention may be configured to generate a number of parity symbols for Reed-Solomon codewords of a particular length constrained by a Galois field of 2
m
, where m is the number of bits per symbol. The present invention is also economical in that it requires a minimum number of logical components to implement and consumes less power, while at the same time being highly configurable. Other advantages of the invention are that it is simple in design, user friendly, robust and reliable in operation, and easily implemented for mass commercial production.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
REFERENCES:
patent: 4852098 (1989-07-01), Brechard et al.
patent: 4888778 (1989-12-01), Brechard et al.
patent: 4907233 (1990-03-01), Deutsch et al.
patent: 5285455 (1994-02-01), Tong et al.
Hahn, “Channel Codec Performs Versatile Error-Correction”, IEE Proceedings, vol. 137, Pt. E, No. 3, May 1990, pp. 197-201.*
Song et al., “Scheduling Strategies for Low-Energy Programmable Digit-Serial Reed-Solomon Codecs”, 1998 IEEE Workshop on Signal Processing Systems, pp. 275-284.*
Wolf, “A DSP Reed-Solomon Coder”, IEEE 1999 Custom Integrated Circuits Conference, pp. 541-544.*
Drescher et al., “VLSI Architecture for Datapath Integration of Arithmetic Over GF(2m) on Digital Signal Processors”, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 631-634.*
Lin, et al., “Error Control Coding, Fundamentals and Applications,” Prentice-Hall, Inc. 1983, pp. 170-176.
Richard A. Blahut, “Theory and Practice of Error Control Codes,” Addison=Wesley Publishing Co., Inc., 1983 pp. 174-191.
Amrany Daniel
Pan Wenwei
Santulli William
Zheng Yue-Peng
Baker Stephen M.
Globespan, Inc.
Thomas Kayden Horstemeyer & Risley
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