Configurable architecture and its implementation of viterbi...

Details Configurable architecture and its implementation of viterbi... Configurable architecture and its implementation of viterbi...

2007-10-02

2007-10-02

Lamarre, Guy J. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S794000, C714S792000, C714S786000, C714S755000, C375S341000, C375S262000, C375S265000, C702S009000

Reexamination Certificate

active

10847911

ABSTRACT:
The present invention relates to a re-configurable Viterbi decoder. By re-setting the values of some registers, the inside control path and data path of the Viterbi decoder can be appropriately changed so as to meet the requirements of different communication systems. The Viterbi decoder comprises a branch metric calculator for receiving data items to be decoded and calculating the branch metrics; an add-compare-select unit for performing an add-compare-select operation on the output of the branch metric calculator and the corresponding path metric; a path metric storage unit (PMS unit) for saving a new path metric produced by the add-compare-select operation in an in-place way; a path memory for storing the shifted out selection bit after the add-compare-select operation; and a trace back unit for reading the selection bit of the path memory so as to perform the feedback decoding.

REFERENCES:
patent: 5502735 (1996-03-01), Cooper
patent: 6690750 (2004-02-01), Hocevar et al.
patent: 7114122 (2006-09-01), Shih
Li et al ‘A new Viterbi decoder design for code rate k
,’ International Conference on Acoustics, Speech, and Signal Processing, ICASSP-95., May 9-12, 1995, vol. 4; pp. 2743-2746.
Li et al ‘A new Viterbi decoder design for code rate k
,’ IEEE, Feb. 1996, vol. 44; pp. 158-164.

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