Concurrent memory control for turbo decoders

Details Concurrent memory control for turbo decoders Concurrent memory control for turbo decoders

2006-01-31

2006-01-31

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S795000

Reexamination Certificate

active

06993704

ABSTRACT:
The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is in marked contrast to conventional turbo decoders which employ either a dual port main memory or a single port main memory in conjunction with a complex ping-ponged scratch memory. In the system of this invention, during each cycle accomplishes one read and one write operation in the scratch memories. If a particular location in memory, has been read, then that location is free. The next write cycle can use that location to store its data. Similarly a simplified beta RAM is implemented using a unique addressing scheme which also obviates the need for a complex ping-ponged beta RAM.

REFERENCES:
patent: 6516444 (2003-02-01), Maru
patent: 6598204 (2003-07-01), Giese et al.
J. Dielissen, et al.;Power-Efficient Layered Turbo Decoder Processor, IEEE Proc. of Conf. Design, Automation and Test in Europe; Los Alamitos, US, 13 Mar. 2001, pp. 246-251.
C. Schurgers, et al.;Energy Efficient Data Transfer and Storage Organization for a MAP Turbo Decoder Module, Proc. 1999 Int'l Symp. On Low Power Electronics and Design, San Diego, CA Aug. 16-17, 1999, pp. 76-81.
J. Vogt, et al.;Comparision of Different Turbo Decoder Realization for LMT-2000, Proc. of the Global Telecommunications Conf. 1999, GLOBECOM '99, vol. 5, Dec. 5, 1999, pp. 2704-2708.

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