Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-07-23
1999-10-26
Chung, Phung M.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714756, 714785, H03M 1300
Patent
active
059745800
ABSTRACT:
An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is carried out by performing iterative passes over the first and second set of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second set codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set codewords are available for immediate processing. In one embodiment, the syndrome buffer stores the error syndromes for both the first and second set codewords so that only one pass over the codewords is necessary to generate the error syndromes. In subsequent passes, the error syndromes are available immediately; they are not regenerated as in the prior art.
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Au Frederick Siu-Huang
Kato Keisuke
Yoon Tony Jihyun
Zook Christopher P.
Chase Shelly A.
Chung Phung M.
Cirrus Logic Inc.
Sheerin Howard H.
Shifrin Dan A.
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