Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-07-17
2011-10-04
Lamarre, Guy (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S785000, C714S807000, C714S819000, C714S758000, C702S189000
Reexamination Certificate
active
08032813
ABSTRACT:
Cyclic redundancy check (CRC) processing is applied to a received sequence of data blocks that are defined by respective sequences of sets of parallel data. For each data block, there is produced a sequence of syndromes that respectively correspond to the sets of parallel data within the data block. The final syndrome in the sequence of syndromes corresponds to all of the data in the data block. The time required for CRC processing can be reduced by concurrently producing first and second ones of the syndromes that respectively correspond to first and second ones of the sets that are respectively contained in first and second ones of the data blocks.
REFERENCES:
patent: 5563896 (1996-10-01), Nakaguchi
patent: 5748652 (1998-05-01), Kim
patent: 6052815 (2000-04-01), Zook
patent: 2002/0046382 (2002-04-01), Yang
Brady III Wade J.
Lamarre Guy
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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