Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-06-18
2002-07-02
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06415413
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to data communications and, more particularly, is related to a Reed-Solomon (“RS”) decoder and method for minimizing or eliminating errors in data communication.
BACKGROUND OF THE INVENTION
Communication of information in the form of digital data is quite commonplace in today's society. There are many different communications channels that may be employed to facilitate such data communication. Such channels may include existing telecommunications networks, optical fiber networks, cellular networks, the Internet, wide area networks, local area networks, or other like media. It is often the case that the communications channels chosen do not provide a perfect medium to transfer data information, and for various reasons such as noise, interference, or other phenomena, errors may be introduced into the data stream transmitted across a particular channel.
Many different approaches have been proposed to either reduce or eliminate errors in data communications. One such approach is to employ Reed-Solomon encoding/decoding. When employing Reed-Solomon encoding/decoding, data is transmitted in codewords which include a number of parity symbols along with the original data symbols. The parity symbols are generated using a Reed-Solomon encoder.
When using Reed-Solomon encoding, various numbers of parity symbols may be generated to allow a data system to correct up to a specific number of possible errors in the transmitted data. However, for each different number of total parity symbols generated, there is a unique Reed-Solomon generator polynomial with a specific number of coefficients employed. Thus, the typical Reed-Solomon encoder creates a specific number of parity symbols, which limits its usefulness if greater or fewer parity symbols are desired. Likewise, Reed-Solomon decoders are employed to correct errors in the transmission using the same specific number of parity symbols which limits its usefulness in the same manner.
SUMMARY OF THE INVENTION
The present invention provides a configurable Reed-Solomon (RS) decoder controller and method employed in an RS decoder that addresses the above concerns. The RS decoder controller comprises a codeword length register to indicate a number of symbols in a number of RS codewords to be decoded by the RS decoder, a error correction capability configuration register to indicate a maximum number of error symbols that can be corrected by the RS decoder, and a modulation scheme associated register to indicate a modulation scheme employed to generate the RS codewords. The RS decoder controller further includes a number of state machines to control the operation of a Galois field computation unit in the RS decoder.
The present invention can also be viewed as providing a method for controlling an RS decoder, comprising the steps of: indicating a number of symbols in a number of RS codewords to be decoded in an RS decoder; indicating a number of error symbols that can be corrected by the RS decoder; indicating a modulation scheme employed to generate the RS codewords; and controlling the operation of a Galois field computation unit in the RS decoder to decode the RS codewords.
A significant advantage of the present invention is that the RS decoder controller is highly configurable to implement Reed-Solomon decoding for different data communications applications, etc. Specifically, the Reed-Solomon decoder controller of the present invention may be configured to control the decoding of Reed-Solomon codewords having various numbers of parity symbols and data symbols. The present invention is also economical in that it requires a minimum number of logical components to implement and is power efficient, while at the same time being highly configurable. Additionally, the unique state machine architecture organization of the RS decoder controller significantly simplifies the implementation and optimizes the required physical decoder area.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
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Pan Wenwei
Zheng Yue-Peng
Baker Stephen M.
GlobespanVirata Inc.
Thomas Kayden Horstemeyer & Risley
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