Architecture for FPGAs
Architecture for implementing two chips in a package
Architecture for local programming of quantum processor...
Architecture for programmable logic device
Architecture for reducing leakage component in semiconductor...
Architecture for routing resources in a field programmable...
Architecture for routing resources in a field programmable...
Architecture of a multiple array high density programmable logic
Architectures for programmable logic devices
Area efficient clock inverting circuit for design for...
Area efficient routing architectures for programmable logic...
Area-efficient implication circuits for very dense Lukasiewicz l
Arithmetic and logic function circuits optimized for datapath la
Arrangement and method for adjustment of the slope times for...
Arrangement and method relating to digital information in...
Arrangement for improving the ESD protection in a CMOS buffer
Arrangement for reducing power dissipation in a line driver
Array of programmable cells with customized interconnections
Arrayed processing element redundancy architecture
ASIC architecture for active-compensation of a programmable...