Architecture of a multiple array high density programmable logic

Details Architecture of a multiple array high density programmable logic Architecture of a multiple array high density programmable logic

1992-08-03

1995-10-10

Nelms, David C.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K 19177

Patent

active

054574099

ABSTRACT:
The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.

REFERENCES:
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4789951 (1988-12-01), Birkner et al.
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 5130574 (1992-07-01), Shen et al.
patent: 5191243 (1993-03-01), Shen et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5220214 (1993-06-01), Pedersen
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
Electronic Engineering, vol. 63, No. 773, May, 1991, London, GB, pp. 69, 70, 72, 74, "Obtaining 70 MHz Performance in the MAX Architecture".
EDN Electrical Design News, vol. 34, No. 20, Sep. 28, 1989, Newton, Mass., US, pp. 91, 93, 94, 96, 98, 100, "PLD Architectures Require Scrutiny".
Electronic Design, vol. 33, No. 25, Oct. 1985, Hasbrouck Heights, N.J., US, pp. 123-128, 130, "Application-Specific IC's Relying on RAM, Implement Almost any Logic Function".
Om P. Agrawal, "AMD's Next Generation MACH.TM. 3xx/4xx Family Breaks New PLD Density/Speed Barrier", Conference Record, Wescon 92, pp. 100-106, Nov. 1992.
Raymond Leung et al., "A 7.5 ns 35O mW BiCMOS PAL.RTM.-type Device," Electronic Engineering, pp. 5.6.1-5.6.4, IEEE 1989 Custom Integrated Circuits Conference.

Affiliated with

Also associated with

Rating

Architecture of a multiple array high density programmable logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture of a multiple array high density programmable logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture of a multiple array high density programmable logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2312836