Arithmetic and logic function circuits optimized for datapath la

Details Arithmetic and logic function circuits optimized for datapath la Arithmetic and logic function circuits optimized for datapath la

1995-12-28

1999-11-09

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326101, 364716, H03K 1900

Patent

active

059821949

ABSTRACT:
A technique for designing circuits with arithmetic or logic functions on integrated circuit devices. The circuit has a primary chain of serially connected logic blocks and secondary chains of serially connected logic blocks. The output node of the last logic block of each secondary chain is connected to an input node of a logic block in the primary chain. Depending upon the desired function, the logic blocks can be logic gates or more complex logic blocks. Zero detect and compare circuits can be designed from this basic arrangement. Connected with input logic, output logic and merge logic, other circuits, including incrementors, decrementors, priority logic, adders and ALUs, are possible. The resulting circuit occupies far less space on an integrated circuit than a fully parallel, lookahead circuit, yet operating speeds are comparable.

REFERENCES:
patent: 4652777 (1987-03-01), Cline
patent: 4879688 (1989-11-01), Turner et al.
patent: 5043988 (1991-08-01), Brglez et al.
patent: 5369314 (1994-11-01), Patel et al.

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