Area efficient routing architectures for programmable logic...

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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C326S038000

Reexamination Certificate

active

07605606

ABSTRACT:
Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.

REFERENCES:
patent: 6462577 (2002-10-01), Lee et al.
patent: 6864713 (2005-03-01), Agrawal et al.
patent: 6970012 (2005-11-01), Crotty et al.
patent: 7000212 (2006-02-01), Agrawal et al.
patent: 7187199 (2007-03-01), Lai
U.S. Appl. No. 11/445,620, filed Jun. 2, 2006, Agrawal et al.
U.S. Appl. No. 11/446,351, filed Jun. 2, 2006, Agrawal et al.
U.S. Appl. No. 11/446,542, filed Jun. 2, 2006, Agrawal et al.
Altera, Section 1, Stratix II Device Family Data Sheet, vol. 1, Jan. 2006, 232 pages.
Xilinx, Virtex-4, Family Overview, DS112, (v1.5) Feb. 10, 2006, 9 pages.
Xilinx, Virtex-II Platform FPGAs: Complete Date Sheet, DS031 (v3.4) Mar. 1, 2005, 318 pages.
Lattice Semiconductor Corporation, LatticeECP/EC Family Data Sheet, Version 02.1, Nov. 2005, 159 pages.
Lattice Semiconductor Corporation, Lattice XP Family Data Sheet, Version 04.2, Mar. 2006, 127 pages.
Altera, Section I. Stratix Device Family Data Sheet, vol. 1, Sep. 2004, 276 pages.
Xilinx, Virtex-E 1.8 V, Field Programmable Gate Arrays, DS022-2 (v2.8) Jan. 16, 2006, 54 pages.
Xilinx, Virtex-4, User Guide, UG070 (v1.4) Sep. 12, 2005, 388 pages.
Xilinx, Spartan-3E FPGA Family: Complete Data Sheet, DS312 May 19, 2006, 230 pages.
Xilinx, Spartan-3 FPGA Family: Complete Data Sheet, DS099 Apr. 26, 2006, 206 pages.

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