Area efficient clock inverting circuit for design for...

Details Area efficient clock inverting circuit for design for... Area efficient clock inverting circuit for design for...

2001-11-16

2003-03-04

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C326S093000, C714S726000, C327S185000

Reexamination Certificate

active

06529033

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits, and more particularly to integrated circuits including both rising edge-triggered circuits to a falling edge-triggered circuits.
BACKGROUND OF THE INVENTION
Modern Integrated Circuits (IC) fabrication processes have reduced the size of transistors such that hundreds of millions of transistors can be inexpensively fabricated on a single semiconductor wafer, or “chip”. This capability has lead to an increased number of different functions performed on a single chip, giving rise to so-called System-On-a-Chip (SOC) devices. For example, a SOC device may include a micro controller (MCU), a digital signal processor (DSP), a reduced instruction set (RISC) processor, memory, and application specific logic circuitry combined on a single chip.
FIG. 1
is a flow diagram illustrating a simplified conventional process for designing and fabricating a SOC device
100
. At the beginning of the design phase, a circuit designer typically selects an IC family that is defined, for example, by the fabrication process and chip size of the completed IC, along with any pre-defined arrangements of transistors and/or contact pads. The user then enters a logic design into a computer or workstation
110
using an input device
111
. Computer
110
is loaded with a logic design entry software tool
113
that is typically linked to a design library
115
containing pre-defined circuit structures and design parameters associated with the selected IC family. Design library
115
also typically includes one or more pre-defined logic elements (often referred to as “macros”) that can be selected by the user during the logic design entry process. The user utilizes entry tool
113
to link these pre-defined logic elements with custom-designed logic elements (if any) to construct the logic design. Once the logic design is entered, place and route tools
117
, also loaded on computer
110
, are utilized to generate a place-and-route solution, which arranges the various interrelated portions of the logic design in an efficient two-dimensional spatial relationship that can be fabricated on a chip, and generates signal lines (interconnect wires) for passing signals between the interrelated portions. A layout tool
119
is then utilized to construct a three-dimensional representation of the actual circuit structures (e.g., regions of doped semiconductor, insulated regions, and metal lines) needed to implement the logic design. The three-dimensional representation is then used to generate a set of masks (step
120
) that are then used to fabricate IC device
100
(step
130
) using known fabrication techniques.
As the number of transistors and functions performed on each chip increases, the possibility of device failure due to fabrication errors also increases. Accordingly, IC manufacturers typically utilize one or more device testing methodologies to test each fabricated device
100
prior to being sold to an end user.
Design-For-Testability (DFT) is one type of standard methodology utilized to test modern ICs, such as SOC device
100
, before sale to an end user. Referring to the lower portion of
FIG. 1
, according to conventional DFT methodology, SOC device
100
is mounted onto a test fixture
140
such that the terminals (contact pads) of SOC device
100
are connected via corresponding wires to a testing station
150
. Testing station
150
(e.g., a computer or workstation) stores one or more DFT software tools
155
that are utilized during testing. One such test performed using DFT tools
155
is referred to as “scan test”, and includes shifting test data values into the device under test (step
142
), causing the device under test to apply the test data to selected internal circuitry (step
144
), and then shifting out the resulting test data (step
146
). The resulting test data is then compared with expected result data to detect erroneous operation of the device under test. If the device under test passes all such testing, the device is then designated for sale to an end user. If the device fails this testing, it is typically discarded.
According to DFT methodology, test data values are serially shifted through a device under test using special (“scan”) flip-flops arranged to form “scan paths”. The scan paths are determined during the design phase of IC production (i.e., steps
113
and
117
, discussed above), and include several scan flip-flops connected in series.
FIG. 2
is a simplified circuit diagram showing an IC device
200
including scan flip-flops FF-
1
and FF-
2
, along with combinational logic circuitry (CLC-
1
and CLC-
2
) and additional circuitry discussed below. Flip-flop FF-
1
has a scan input TI connected to receive a TEST value, a data input terminal D for receiving a DATA value, a clock terminal (>) connected to receive a clock signal CLK
1
, a data output terminal Q, and a scan enable terminal TE connected to receive a mode control signal MC. Similarly, flip-flop FF-
2
has a scan input TI connected to the output terminal of flip-flop FF-
1
by a scan path portion
201
, a data input terminal D connected to receive a data value from combinational logic circuit CLC-
1
, a clock terminal (>), a data output terminal Q, and a scan enable terminal TE connected to receive mode control signal MC. Scan flip-flops FF-
1
and FF-
2
are constructed to operate in either a test mode or a normal operation mode, which is determined by mode control signal MC. During the test mode (e.g., mode control signal MC is asserted), each scan flip-flop FF-
1
and FF-
2
stores test data received from a preceding scan flip-flop in a scan path, thereby allowing test data values to be shifted along the scan path. For example, during the test mode, flip-flop FF-
2
registers (stores) the test value passed from flip-flop FF-
1
to its scan input terminal TI on scan path portion
201
. Accordingly, the scan paths are utilized to pass test data into a device under test during test data input (step
142
), and also to pass resulting test data out of the device during subsequent data output procedures (step
146
). During normal operations (e.g., mode control signal MC is de-asserted), the scan flip-flops receive and store data values applied to data input terminals D. For example, during normal operation, flip-flop FF-
2
registers data values generated by logic circuit CRC-
1
.
Conventional DFT tools (such as DFT tool
155
; see
FIG. 1
) are typically purchased by an IC manufacturer from a company that specializes in producing such tools. For example, third-party DFT tools are commercially available from Mentor Graphics of Wilsonville, Oreg., and Synopsis Inc. of Sunnyvale, Calif. Such DFT tools facilitate testing by providing a test clock signal (e.g., CLK-
1
in
FIG. 2
) supplied to the scan flip-flops (and other clocked elements) of a device under test during the test mode, and input/output circuitry for transmitting test data to and resulting data from the device under test. A problem associated with these currently available DFT tools arises when an IC manufacturer's device includes both rising edge-triggered flip-flops and falling edge-triggered flip flops are utilized in an IC device. In particular, difficulties arise when a single clock signal is used to control both rising edge-triggered circuits and falling edge-triggered circuits during scan testing. For example, it both rising edge-triggered scan flip-flops and falling edge-triggered scan flip-flops are incorporated into the same scan path and driven by the same clock signal, then test data cannot be scanned (serially passed) using existing DFT tools. To circumvent this limitation of the DFT tools, IC manufacturers must devise test strategies that allow testing of the circuitry connected to both types of flip-flops.
Referring again to
FIG. 2
, simplified IC device
200
is modified according to one conventional method to facilitate testing both rising edge-triggered flip-flops (e.g., flip-flops FF-
1
and FF-
2
) and falling edge-triggered flip-flops (e.g., FF-
3
) usin

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