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Semiconductor logic circuit device having pull-up/pull-down...

Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate

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Single clock source for plural scan capture chains

Electronic digital logic circuitry – With test facilitating feature
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Static current testing apparatus and method for current steering

Electronic digital logic circuitry – With test facilitating feature
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Structure for externally identifying an internal state of a semi

Electronic digital logic circuitry – With test facilitating feature
Patent

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Switchable pull-ups and pull-downs for IDDQ testing of integrate

Electronic digital logic circuitry – With test facilitating feature
Patent

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System and method for observing information transmitted...

Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate

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System and method for testing integrated circuits connected toge

Electronic digital logic circuitry – With test facilitating feature
Patent

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System on chip (SOC) and method of testing and/or debugging...

Electronic digital logic circuitry – With test facilitating feature
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Systems and methods for maintaining board signal integrity

Electronic digital logic circuitry – With test facilitating feature
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Test circuit for semiconductor integrated logic circuit using tr

Electronic digital logic circuitry – With test facilitating feature
Patent

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Test mode circuit of semiconductor device

Electronic digital logic circuitry – With test facilitating feature
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Test structures for simultaneous switching output (SSO)...

Electronic digital logic circuitry – With test facilitating feature
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Testing hot carrier induced degradation to fall and rise time of

Electronic digital logic circuitry – With test facilitating feature
Patent

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Tie-up and tie-down circuits with a primary input for testabilit

Electronic digital logic circuitry – With test facilitating feature
Patent

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Verify scheme for a multi-level routing structure

Electronic digital logic circuitry – With test facilitating feature
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