System and method for testing integrated circuits connected toge

Details System and method for testing integrated circuits connected toge System and method for testing integrated circuits connected toge

1997-09-19

1998-12-22

Santamauro, Jon

Electronic digital logic circuitry

With test facilitating feature

371 221, 371 2231, H03K 1900, G01R 3128

Patent

active

058523642

ABSTRACT:
An integrated circuit includes a terminal which is accessible externally of the integrated circuit, and circuitry (LOB) coupled to said terminal and operable to latch at said terminal a signal applied to said terminal by a source (ICT) external to said integrated circuit.

REFERENCES:
patent: 4669061 (1987-05-01), Bhavsar
patent: 4864579 (1989-09-01), Kishida et al.
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5134314 (1992-07-01), Wehrmacher
patent: 5317205 (1994-05-01), Sato
patent: 5450415 (1995-09-01), Kamada
patent: 5526310 (1996-06-01), Dondale
David George, "Use a Reprogrammable Approach to Boundary Scan for FPGAs", EDN Electrical Design News, vol. 38, No. 16, 5 Aug. 1993, pp. 97-100.

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