Test circuit for semiconductor integrated logic circuit using tr

Electronic digital logic circuitry – With test facilitating feature

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Details

H03K 1900

Patent

active

060284439

ABSTRACT:
In a semiconductor integrated logic circuit including a tri-state output buffer having three different output conditions of a logical high level, a logical low level and a high impedance condition, and an internal control circuit generating a control signal for controlling the tri-state output buffer, a first selector is provided which has a first input receiving a data signal outputted from an internal logic circuit, a second input connected to receive the control signal, and an output connected to an data input of the tri-state output buffer. A second selector is provided which has a first input connected to receive the control signal, and a second input connected to a logic high level which brings the tri-state buffer into an output enable condition in which the tri-state output buffer outputs either the logical high level or the logic low level. An output of the second selector is connected to a control input of the tri-state output buffer. A common switch signal is supplied in common to an selection control input of each of the first and second selectors. When the common switch signal is indicative of a test mode, the first selector selects and outputs the control signal to the data input of the tri-state output buffer and the second selector selects and outputs the logic high level to the control input of the tri-state output buffer so that the tri-state buffer is brought in the output enable condition so as to output the control signal.

REFERENCES:
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patent: 5136185 (1992-08-01), Fleming et al.
patent: 5159263 (1992-10-01), Yaguchi
patent: 5285119 (1994-02-01), Takahashi
patent: 5561614 (1996-10-01), Revilla et al.
patent: 5671233 (1997-09-01), Kamada

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