Electronic digital logic circuitry – With test facilitating feature
Patent
1995-09-26
1997-07-01
Westin, Edward P.
Electronic digital logic circuitry
With test facilitating feature
326 39, 371 221, H03K 1900
Patent
active
056442513
ABSTRACT:
An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.
REFERENCES:
patent: 5371457 (1994-12-01), Lipp
patent: 5467026 (1995-11-01), Arnold
patent: 5475330 (1995-12-01), Watanabe et al.
Abrishami Ray
Colwell Michael
Rajsuman Rochit
Sarkari Zarir B.
LSI Logic Corporation
Roseen Richard
Westin Edward P.
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