Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2007-06-12
2007-06-12
Cho, James (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C714S727000
Reexamination Certificate
active
10964928
ABSTRACT:
In a semiconductor logic circuit device including an internal circuit, a group of first pads, a group of second pads, and a plurality of input buffers, each connected between the internal circuit and one of the first and second pads, for supplying input signals from their corresponding pads to the internal circuit, each of the first pads is connected to at least one of a pull-up circuit for pulling up a voltage at each of the first pads to a first voltage, and a pull-down circuit for pulling down the voltage at each of the first pads to a second voltage lower than the first voltage.
REFERENCES:
patent: 5115191 (1992-05-01), Yoshimori
patent: 5644251 (1997-07-01), Colwell et al.
patent: 5670890 (1997-09-01), Colwell et al.
patent: 5757820 (1998-05-01), Angelotti
patent: 6539511 (2003-03-01), Hashizume
patent: 2001/0052095 (2001-12-01), Ryan et al.
patent: 2004/0128596 (2004-07-01), Menon et al.
patent: 58-118123 (1983-07-01), None
patent: 07-84009 (1995-03-01), None
European Office Action dated Jun. 2, 2005.
European Search Report dated Feb. 4, 2005.
Cho James
Crawford Jason
McGinn IP Law Group PLLC
NEC Electronics Corporation
LandOfFree
Semiconductor logic circuit device having pull-up/pull-down... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor logic circuit device having pull-up/pull-down..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor logic circuit device having pull-up/pull-down... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3866639