Architecture for routing resources in a field programmable...
Architecture of a multiple array high density programmable logic
Architectures for programmable logic devices
Area efficient routing architectures for programmable logic...
Arithmetic and logic function circuits optimized for datapath la
Array of programmable cells with customized interconnections
Asynchronous latch design for field programmable gate arrays
Automatic disabling of SCSI bus terminators
Automatic enabling/disabling of termination impedance for a comp
Balanced-delay programmable logic array and method for...
Base cell and two-dimensional array of base cells for...
Basic cell structure having a plurality of transistors for maste
Bi-directional crossbar switch with control memory for selective
Bi-directional programmable I/O cell
Bidirectional register segmented data busing
Block clock and initialization circuit for a complex high densit
Block connector splitting in logic block of a field...
Block connector splitting in logic block of a field...
Block connector splitting in logic block of a field...
Block RAM with configurable data width and parity for use in...