Block clock and initialization circuit for a complex high densit

Details Block clock and initialization circuit for a complex high densit Block clock and initialization circuit for a complex high densit

1996-11-05

1998-09-22

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 38, H03K 738

Patent

active

058119876

ABSTRACT:
A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.

REFERENCES:
patent: 5598112 (1997-01-01), Phillips
patent: 5670896 (1997-09-01), Diba et al.

Affiliated with

Also associated with

Rating

Block clock and initialization circuit for a complex high densit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block clock and initialization circuit for a complex high densit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block clock and initialization circuit for a complex high densit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1625752