Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2001-06-12
2003-09-23
Le, Don (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06624657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field programmable gate array (FPGA) architecture. More particularly, the present invention relates to the routing resources within a logic block for increasing the routing flexibility in an FPGA architecture.
2. The Background Art
In the FPGA art, both antifuse based programmable architectures and SRAM based reprogrammable architectures are well known. In an FPGA, the logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. In a antifuse based device, the number of the programmable elements far exceeds the number of elements in an SRAM based device because the area required for an antifuse is much smaller than an SRAM bit. Despite this space disadvantage of an SRAM based device, SRAM based devices are implemented because they are reprogrammble, whereas an antifuse device is presently one-time programmable.
Due to the area required for an SRAM bit, a reprogrammble SRAM bit cannot be provided to connect routing resources to each other and the logic elements at every desired location. The selection of only a limited number of locations for connecting the routing resources with one another and the logic elements is termed “depopulation”. Because the capability to place and route a wide variety of circuits in an FPGA depends upon the availability of routing and logic resources, the selection of the locations at which the programmable elements should be made with great care.
Some of the difficulties faced in the place and route caused by depopulation may be alleviated by creating symmetries in the FPGA. For example, look-up tables (LUT) are often employed at the logic level in an SRAM based FPGA, because a LUT has perfect symmetry among its inputs. The need for greater symmetry in a reprogrammable FPGA architecture does not end with the use of look-up tables. It also extends to the manner in which routing resources are connected together and the manner in which routing resources are connected to the logic elements. Without a high degree of symmetry in the architecture, the SRAM memory bit depopulation makes the place and route of nets in an SRAM based FPGA difficult.
As FPGAs have grown in size and complexity, the logic elements have typically been grouped into blocks which contain multiple combinatorial and sequential logic blocks that share interconnection and have local interconnect conductors for use inside the block. In these blocks, the inputs and outputs to the blocks are typically accessible to the general routing resources of the FPGA from at least two sides of the block, and sometimes from all four sides of the block.
Some inputs and outputs are accessible from more than one side of the block. An input or output that is accessible from more than one side of the block can provide a greater degree of flexibility for placing and routing the FPGA. For this reason, despite the fact that providing an input or output that is accessible from more than one side of the block requires additional silicon area, this feature is quite desirable. Typically, the routing conductors that provide access from two sides are pairwise shorted to essentially provide 2N access ports for each of the N shorted interconnect conductors. Although this increases flexibility, it is also wasteful, because in the majority of cases a connection to the general routing resources is made in a horizontal or vertical direction, but not both.
It is therefore an object of the present invention to provide the flexibility achieved by the routing conductors that provide access from two sides which are pairwise shorted, but eliminates the waste and also provide additional flexibility.
BRIEF DESCRIPTION OF THE INVENTION
The present invention is directed to aspects of a semi-hierarchical architecture in an FPGA having top, middle and low levels. In a semi-hierarchical architecture according to the present invention, the three levels of the architecture may be coupled to one another in a hierarchical or semi-hierarchical manner and the routing resources in each of the three levels may be extended to similar architectural groups in the same level of the architecture. The FPGA architecture according to the present invention has structures for connecting the routing resources in the FPGA to one another to improve the symmetry of the FPGA architecture and thereby increase the place and routability of an FP GA.
The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. The width freeway routing channel in the rectangular array can be changed to accommodate different numbers of B16×16 tiles without disturbing the internal structure of the B16×16 tiles. The freeway routing channels can be extended in any combination of directions at each end by a freeway turn matrix (F-turn).
A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B1 blocks. The B2×2 tiles are stepped into a four by four array of sixteen B1 blocks in a B4×4 tile, and the B4×4 tiles are stepped into a eight by eight array of sixty-four B1 blocks in a B8×8 tile. A B16×16 tile includes four B8×8 tiles.
The routing resources in the middle level of hierarchy are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. The expressway routing channels M1, M2, and M3 are segmented, and between each of the segments in the expressway routing channels M1, M2, and M3 are disposed extensions that can extend the expressway routing channel M1, M2, or M3 an identical distance along the same direction. The extensions that couple the segments in the expressway routing channels M1 and M2 provide a one-to-one coupling between the interconnect conductors of the expressway routing channels M1 and M2 on either side of the extensions. The segments of an M3 expressway routing channel is extended at the boundary of a B16×16 tile where an expressway routing channel M3 crosses a freeway routing channel by a freeway tab (F-tab), and otherwise by an M3 extension. At the intersection of M1, M2, and M3 routing resources traversing a first direction with M1, M2, and M3 routing resources traversing a second direction are disposed expressway turns (E-turn).
At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors.
A B1 block is at the lowest level in the FPGA architecture. Each B1 block includes four clusters of devices. Each of the four clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have first, second, and third inputs and a single output. Each of the LUT2s have first and second inputs and a single output. With a LUT3 any three input Boolean logic function may be implemented, and with a LUT2 any two input Boolean logic function may be implemented. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are muliplexed to the input of the DFF to form first and second outputs of each of the clusters.
Within the B1 block, a horizontal BC routing channel is disposed between two upper clusters and two lower clusters, and a vertical BC routing channel is disposed between two clusters on the left side of the B1 block and two clusters on the right side of the B1 block. The horizontal BC routing channel forms a first diagonally hardwired connection with a routing channel that effectively sends the horizontal BC routing channel in a vertical direction. A second diagonally hardwired connection pairwise shorts
Actel Corporation
Le Don
Sierra Patent Group Ltd.
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