Global signal distribution with reduced routing tracks in an FPG
GPIO mux/dynamic port configuration
Hard macro-to-user logic interface
Hardening logic devices
Heterogeneous CPLD logic blocks
Heterogeneous labs
Hi-speed parallel configuration of programmable logic
Hierarchical interconnect for programmable logic devices
Hierarchically connectable configurable cellular array
Hierarchically connectable configurable cellular array
Hierarchically-structured programmable logic array and system fo
High bandwidth reconfigurable on-chip network for...
High density and high speed magneto-electronic logic family
High density antifuse based partitioned FPGA architecture
High density antifuse based partitioned FPGA architecture
High density PLD structure with flexible logic built-in blocks
High density programmable logic device
High fan-out signal routing systems and methods
High performance product term based carry chain scheme
High performance product term based carry chain scheme