High density PLD structure with flexible logic built-in blocks

Details High density PLD structure with flexible logic built-in blocks High density PLD structure with flexible logic built-in blocks

1998-01-15

2000-08-08

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, 326 41, 326 47, H03K 19177, H03K 19173

Patent

active

061007145

ABSTRACT:
A programmable logic device (PLD) includes logic built-in blocks (LBB) connected with a programmable interconnection array (PIA). Each LBB has two configurable logic cells sharing a group of control product terms, which serve as global and local control signals. Each configurable logic cell employs a programmable array (an AND gate array connected to two OR gate arrays), followed by two groups of Multi-Register Macro Cells (MRMC). The multi-register macro cells contain registers, which are grouped into logic control cells, multiplexers and I/O cells. The registers receive sum terms from the OR gate arrays as inputs, while the multiplexers direct the flow of the outputs and feedbacks, which can be either latched outputs from registers or direct sum terms from the OR gate arrays. All of the controls of the multi-register macro cells in an LBB are available from shared control product terms, thus providing both local and global control signals. This PLD architecture achieves high density, high performance and great flexibility, while using less memory than current PLDs.

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