Hardening logic devices

Details Hardening logic devices Hardening logic devices

2005-03-08

2005-03-08

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S047000, C326S016000, C326S101000

Reexamination Certificate

active

06864712

ABSTRACT:
The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.

REFERENCES:
patent: 5587921 (1996-12-01), Agrawal et al.
patent: 5805496 (1998-09-01), Batson et al.
patent: 5818750 (1998-10-01), Manning
patent: 6301696 (2001-10-01), Lien et al.

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