Heterogeneous CPLD logic blocks

Details Heterogeneous CPLD logic blocks Heterogeneous CPLD logic blocks

2000-03-15

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S038000

Reexamination Certificate

active

06320410

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to Complex Programmable Logic Devices (CPLDs) generally and, more particularly, to a circuit, method and architecture for optioning the density of a CPLD to provide convenient design migration.
BACKGROUND OF THE INVENTION
CPLD families may have a variety of variations such as multiple densities, multiple packages, multiple voltages and multiple speeds. Referring to
FIG. 1
, a CPLD having 16 logic blocks with each logic block having 16 I/Os is shown. An example of such a CPLD can be found in “Programmable Logic Data Book 1996 (and 1997)” by Cypress Semiconductor Corp., which is hereby incorporated by reference in its entirety. The following TABLE 1 illustrates some of the density and package combinations offered within a particular family:
TABLE 1
Part
Macrocells
I/O Pins
32P44
32
32
64P44
64
32
64P84
64
64
128P84 
128
64
128P160
128
128
192P160
192
120
256P160
256
128
256P208
256
160
256P256
256
192
384P208
384
160
384P256
384
192
512P208
512
160
512P256
512
192
512P352
512
256
As shown in TABLE 1, there are several instances where two different densities are offered with the same number of I/O pins. The first example is the 32P44 and the 64P44. The 32P44 has half the macrocell density of the 64P44, while both have 32 I/O pins. Both parts are available in identical packages with identical pin definitions, thus allowing either part to be used in the same physical location in a board or system design. This characteristic of a family may enable design migration (i.e., the ability for customers to migrate a design to a different density while keeping the same footprint on their printed circuit board).
Providing design migration requires that a given density be offered with multiple I/O configurations. An example from TABLE 1 is the 256-macrocell density being offered with 128, 160, and 192 I/Os. These different I/O configurations are almost always implemented by completing one base design that can be optioned to generate the different configurations required. The optioning is usually done as a mask option, bond option, or programming option.
Additionally, the implementation may allow two different densities to be included in the same base design with optioning provided to generate the two densities. As an example, the 192-macrocell and 256-macrocell designs can be implemented as one base design with a metal mask option to differentiate the two densities. The different I/O options of the 256 macrocell part for 128, 160, and 192 I/Os can then be accomplished with bond options in the appropriate packages.
The method of optioning a base design to offer multiple device densities may not be used in all CPLD designs. Offering a device with a number of macrocells that are less than the total number of macrocells on the die is more costly in silicon. However, such an approach may reduce the overall design and production costs by reducing the overall number of parts that have to be designed and produced.
From a software perspective, it is generally advantageous to have homogeneous logic blocks of a particular density and package. Part of this homogeneity is having the same number of I/Os in each of the logic blocks. The advantage to the software comes in the partitioning portion of fitting a design, since having identical logic blocks allows like sections of a design to be known to fit into any of the available logic blocks. This advantage is sometimes taken away by the user of the CPLD as a user can choose to reserve pins for future use, thus removing the natural homogeneity included.
One conventional approach for optioning a base design to offer a smaller device density with the same number of I/Os is to completely disable some logic blocks while at the same time increasing the number of I/O macrocells in the logic blocks that remained enabled.
Such a conventional method is explained in connection with the following TABLE 2. The CPLD illustrated has 16 logic blocks with 16 macrocells in each logic block. The physical layout is organized with eight logic blocks on the left and eight on the right. TABLE 2 shows the 16 logic blocks of a particular design, with the number of I/O macrocells that are contained within each logic block.
TABLE 2
192
256
256
256
Logic
Logic
256
256
256
192
P160
P256
P208
P160
Block
Block
P160
P208
P256
P160
10
12
10
8
A
P
8
10
12
10
10
12
10
8
B
O
8
10
12
10
(dis)
12
10
8
C
N
8
10
12
(dis)
10
12
10
8
D
M
8
10
12
10
10
12
10
8
E
L
8
10
12
10
(dis)
12
10
8
F
K
8
10
12
(dis)
10
12
10
8
G
J
8
10
12
10
10
12
10
8
H
I
8
10
12
10
For the 256P160, which has 128 I/Os, each of the 16 logic blocks has eight I/O macrocells, thus generating the 128 total I/O macrocells. For the 256P208, which has 160 I/Os, each of the 16 logic blocks has ten I/O macrocells, thus generating the 160 total I/O macrocells. For the 256P256, which has 192 I/Os, each of the 16 logic blocks has 12 I/O macrocells, thus generating the 192 total I/O macrocells.
For the 192P160, four of the logic blocks are completely disabled (i.e., the logic blocks C, F, K, and N). The remaining 12 logic blocks are enabled each having 10 I/O macrocells, which generates 120 I/O macrocells. Comparing the 256P160 to the 192P160 shows that four logic blocks have been disabled while the number of I/O macrocells in a logic block has been increased from eight on the 256P160 to 10 on the 192P160.
The 192P160 and the 256P160 are two density and package combinations that are intended to allow design migration. As TABLE 2 shows, the 192P160 provides 120 I/Os while the 256P160 provides 128 I/Os. This allows reasonable design migration, but not the ideal solution. The problem stems from the 256P160 and 192P160 having 16 and 12 logic blocks, respectively, while each trying to provide 128 I/Os. 128 I/Os divided by 16 logic blocks is exactly 8, so the 256P160 provides 128 I/Os with homogeneous logic blocks. However, 128 I/Os divided by 12 logic blocks is not an integer, so the 192P160 can provide either 120 I/Os or 132 I/Os with homogeneous logic blocks.
Also, because of the constraints of the global signals within a logic block, like the block reset, block preset, or block product term clock, some of the 192P160 designs will not fit into the 256P160, thus not allowing design migration.
SUMMARY OF THE INVENTION
The present invention concerns a programmable logic device comprising a first plurality of logic blocks each comprising a first number of I/O macrocells, a second plurality of logic blocks each comprising a second number of I/O macrocells and a configuration circuit configured to enable one or more of said first plurality of logic blocks and/or one or more of said second plurality of logic blocks.
The objects, features and advantages of the present invention include providing a logic device that may (i) offer design migration by including the same number of I/Os in a higher density device as a lower density device, (ii) include heterogeneous logic blocks, (iii) include one set of logic blocks having zero I/O macrocells and/or (iv) include one set of logic blocks having a homogeneous non-zero number of macrocells.


REFERENCES:
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patent: 5848285 (1998-12-01), Kapusta et al.
patent: 5963048 (1999-10-01), Harrison et al.
patent: 6100714 (2000-08-01), Xiao et al.
patent: 6150841 (2000-11-01), Agrawal et al.
patent: 6198305 (2001-03-01), Skahill et al.
Cyress Programmable Logic Data Book, 1997, pp. 3-34 through 3-59.

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