P-domino output latch

P-domino register

Partial swing low power CMOS logic circuits

PMOS charge-sharing prevention device for dynamic logic circuits

Polyphase clock generation circuit

Power reduction circuits and systems for dynamic logic gates

Power saving clock buffer

Power supply switching at circuit block level to reduce...

Power-saving dynamic circuit

Pre-charge triggering to increase throughput by initiating regis

Programmable timing boundary in dynamic circuits

Pseudo CMOS dynamic logic with delayed clocks

Pseudo CMOS dynamic logic with delayed clocks

Pseudo-CMOS dynamic logic with delayed clocks

Pseudo-dynamic latch deracer

Pseudofooter circuit for dynamic CMOS (Complementary...

Pulse evaluate logic-latch

Pulsed circuit topology including a pulsed, domino flip-flop

Pulsed dynamic keeper gating

Pulsed reset single phase domino logic