Pseudo-dynamic latch deracer

Details Pseudo-dynamic latch deracer Pseudo-dynamic latch deracer

2005-04-12

2005-04-12

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000

Reexamination Certificate

active

06879186

ABSTRACT:
An apparatus and method for a pseudo-dynamic latch are disclosed. A deracer circuit includes a first logic gate configured to receive a data signal from a domino logic circuit and to invert the data signal. A second logic gate is configured to receive the inverted data signal and an inverted select signal and to generate a select signal. Thus, the deracer circuit is configured to prevent the select signal from being high when a precharge edge of a data signal arrives.

REFERENCES:
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 6542006 (2003-04-01), Sprague et al.
patent: 6677783 (2004-01-01), Samaan

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