Pulsed reset single phase domino logic

Details Pulsed reset single phase domino logic Pulsed reset single phase domino logic

1996-08-27

1998-10-27

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 17, 326 97, H03K 19096

Patent

active

058282343

ABSTRACT:
The pulsed reset single phase dynamic logic of the present invention reorders the conventional modes of operation such that in a single cycle of operation of a domino logic circuit, reset occurs first, followed sequentially by gap2, evaluation and gap1. To reset each domino stage prior to evaluating, a reset pulse is propagated to each domino stage, with an evaluate signal arriving at each stage as the reset pulse is ending. The circuit configuration of the present invention creates a different, but shorter and easier to manage set of race conditions. The present invention permits the creation of faster and more robust circuit designs.

REFERENCES:
patent: 4700088 (1987-10-01), Tubbs
patent: 5402012 (1995-03-01), Thomas
patent: 5440243 (1995-08-01), Lyon
patent: 5565798 (1996-10-01), Durham et al.

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