Pseudo CMOS dynamic logic with delayed clocks

Details Pseudo CMOS dynamic logic with delayed clocks Pseudo CMOS dynamic logic with delayed clocks

2005-12-06

2005-12-06

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C365S203000

Reexamination Certificate

active

06972599

ABSTRACT:
Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region of at least two input transistors. The dynamic pseudo-pMOS logic gate includes a delayed enable clock transistor coupled to a drain of at least two input transistors. None of the logic input devices are connected in series.

REFERENCES:
patent: 4831285 (1989-05-01), Gaiser
patent: 5258666 (1993-11-01), Furuki
patent: 5315301 (1994-05-01), Hosotani et al.
patent: 5467026 (1995-11-01), Arnold
patent: 5670898 (1997-09-01), Fang
patent: 5821778 (1998-10-01), Bosshart
patent: 5825208 (1998-10-01), Levy et al.
patent: 5926487 (1999-07-01), Chappell et al.
patent: 5999019 (1999-12-01), Zheng et al.
patent: 6208907 (2001-03-01), Durham et al.
patent: 6265897 (2001-07-01), Poirier et al.
patent: 6362645 (2002-03-01), Hayakawa
patent: 6373290 (2002-04-01), Forbes
patent: 6466057 (2002-10-01), Naffziger
patent: 6549038 (2003-04-01), Sechen et al.
patent: 6563345 (2003-05-01), Forbes
patent: 6597203 (2003-07-01), Forbes
patent: 6624686 (2003-09-01), Gedamu et al.
patent: 6649476 (2003-11-01), Forbes
patent: 6664813 (2003-12-01), McCurdy et al.
patent: 2002/0110032 (2002-08-01), Forbes
patent: 2002/0130685 (2002-09-01), Forbes
patent: 2002/0130686 (2002-09-01), Forbes
patent: 2003/0049910 (2003-03-01), Forbes
patent: 2003/0076721 (2003-04-01), Forbes
patent: 2003/0153156 (2003-08-01), Forbes
patent: 2003/0206037 (2003-11-01), Forbes
patent: 2003/0227072 (2003-12-01), Forbes
Krause, M A., et al., “Programmable logic array structures for CMOS VLSI”,International Electrical, Electronics Conference Proceedings, (1983), Abstract.
McMurchie, Larry, et al., “Output Prediction Logic: a High-Performance CMOS Design Technique”,Computer Design, (2000), pp. 247-254.
Rabaey, JM., “Digital integrated circuits, a design perspective”, (1996), pp. 205-209.
Rajsuman, R, et al., “CMOS stuck-open fault detection using single test patterns”,26th ACM/IEEE Design Automation Conference, (1989), Abstract.
Sakamoto, H., “Grounded Load Complementary FET Circuits: Sceptre Analysis”,IEEE Journal of Solid-State Circuits, vol. SC-8, No. 4., (Aug. 1973), pp. 282-284.
Subba, N, et al., “Pseudo-nMOS revisited: impact of SOI on low power, high speed circuit design”,IEEE International SOI Conference, (2000), Abstract.
Sun, Sheng, et al., “A High-Performance 64-bit Adder Implemented in Output Prediction Logic”,Advanced Research in VLSI, (2001), pp. 213-222.

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