P-domino register

Details P-domino register P-domino register

2007-03-06

2007-03-06

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C327S215000

Reexamination Certificate

active

11251384

ABSTRACT:
A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.

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