Pulse evaluate logic-latch

Details Pulse evaluate logic-latch Pulse evaluate logic-latch

2005-03-01

2005-03-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000

Reexamination Certificate

active

06861876

ABSTRACT:
A pulse clock is generated by a pulse generator from a system clock. This pulse determines when the output of a high fan-in gate is to be latched. The pulse clock also feeds a latch with no pass gate and sets the timing of the high fan-in dynamic gate. Because of the length of the active time of the pulse clock, the high fan-in dynamic gate does not have a holder.

REFERENCES:
patent: 5532625 (1996-07-01), Rajivan
patent: 5936449 (1999-08-01), Huang
patent: 6377078 (2002-04-01), Madland
patent: 6393446 (2002-05-01), Dhong et al.
patent: 6433577 (2002-08-01), Wang et al.
patent: 6496038 (2002-12-01), Sprague et al.
patent: 6529045 (2003-03-01), Ye et al.

Affiliated with

Also associated with

Rating

Pulse evaluate logic-latch does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pulse evaluate logic-latch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pulse evaluate logic-latch will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3438978