Power saving clock buffer

Details Power saving clock buffer Power saving clock buffer

1999-05-03

2000-12-12

Nguyen, Viet Q.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

365233, H03K 19003

Patent

active

061604224

ABSTRACT:
A power saving clock buffer comprises a first control stage installed between a clock output and a first switch stage for controlling the state of the first switch stage. A second switch stage installed between the clock output and a second switch stage for controlling the state of the second switch stage. A clock input stage is formed by connecting an PMOS with a NMOSs, and is installed between a clock input and the first and second switch stages and is connected to the clock output through a phase inverting logic circuit. By the aforementioned circuit structure, the clock circuit will stop working as the related circuit does not work and, therefore, the power is saved and a high reliability is attained.

REFERENCES:
patent: 5087841 (1992-02-01), Rogers
patent: 5452434 (1995-09-01), MacDonald
patent: 5760620 (1998-06-01), Doluca

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