Programmable timing boundary in dynamic circuits

Details Programmable timing boundary in dynamic circuits Programmable timing boundary in dynamic circuits

2000-04-03

2002-10-08

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S093000, C326S097000, C326S098000, C326S112000

Reexamination Certificate

active

06462581

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to the field of integrated circuits and more particularly relates to a method and apparatus to inserting a programmable delay in dynamic circuits.
BACKGROUND OF THE INVENTION
The endeavor for faster and faster circuits have reached remarkable milestones since their inception and coming of age during the past sixty years, especially logic circuits in connection with the development of computers. The beginning of the computer age was characterized by connecting vacuum tubes with large coaxial cables for wiring analog logic. If a new problem was to be solved, the cables were reconfigured. Today, coaxial cables have been replaced with high speed data buses; vacuum tubes have been replaced with high speed logic circuits whose transistors are fabricated from new semiconductor materials and designs, all of which are limited only by the laws of physics.
While much work has been done in the arrangement of parts of a computer by, e.g., bringing memory closer to the processor and incorporating cache memories, etc., the real determination of how fast or how slow a computer is is dependent upon the circuit elements at the electronic level. Transistors themselves have become faster and a major aspect of circuit design is fine-tuning the delays associated with numerous signals to make the circuit as fast as possible and yet still maintain spatial and heat dissipation requirements.
Delay simply refers to a signal not arriving when it is expected, whether it be a clock signal or a data signal. In fact, hardware delays are often intentionally inserted into a complex circuit design to synchronize the arrival or evaluation of a particular signal in one part of the circuit with another part of the circuit, or to synchronize the arrival of two signals. The insertion of intentional delays is a critical aspect of circuit design. The problem of the precision of the delay predicted by computerized design models versus the delay in the actual manufactured hardware is described by the term “hardware-to-model correlation.” If the models predict the delays of the hardware closely, then the hardware-to-model correlation is said to be good. If, however, the hardware delays don't match the predicted simulation delays then the hardware-to-model correlation is poor. In actuality, it is not possible to create exact models for delay that match the hardware and sometimes hardware-to-model correlation can be quite bad. This is particularly true with new technologies like silicon-on-insulator (SOI) technology or even with fast versions of traditional bulk CMOS technology.
A critical path simply refers to the slowest path through a circuit and usually starts and ends with a latch boundary, a latch being the hardware to store or evaluate a single bit. Especially with the newer technologies, a critical path can be slower than predicted by the models significantly hampering the maximum performance of the system. All too often, moreover, poor correlation isn't discovered until testing the hardware after it has been fabricated and then it is too late to change the timing delay. A designer knows that not every signal path is a critical path and in a standard distribution of timing paths of circuits, the critical paths are on the slow end of the bell curve. From experience and computer simulation modeling, moreover, a designer also knows where the critical paths are and delays can be removed or inserted into other synchronizing paths during the design. In cases, however, where one critical path feeds another critical path it is difficult to know which path is slower because of inaccurate modeling. The designer may not know whether to take logic out of one path and place it in the other or vice versa in order to achieve a speedup because the delays cannot be reasonably predicted.
One such technology that is capable of achieving high speeds and high density of electronic components in custom integrated circuit design is dynamic CMOS. Dynamic CMOS differs from static CMOS because whereas static CMOS incorporates pull-up and pull-down transistor networks to calculate whether an input signal is a digital “1” or a digital “0”, dynamic CMOS uses parasitic capacitance, previously considered detrimental in static CMOS, to advantage. In dynamic CMOS, the output node of a combinational logic gate is precharged to a voltage, Vdd, just prior to the evaluation of the logic function and may be conditionally discharged to ground using only one pull-down network, depending on the particular values of input signals. If the inputs are such that the logic function should be a logical “0”, then the pull-down output node turns ON and the precharged voltage is discharged quickly to ground. If the inputs are such that the logic function should be “1”, the pull-down output node remains OFF and at Vdd.
Several stages of these dynamic CMOS field effect transistors can be configured into a circuit called domino logic because like a row of closely-spaced dominos which have been stood on end, once a signal enters the first latch the signal quickly propagates or cascades to all other circuit elements in the domino circuit like all the other dominos falling once the first domino has been tipped. The first stage of a domino circuit typically comprises a precharge device, typically a p-type field effect transistor (pfet) whose drain is connected to a pull-down network of n-type field effect transistors (nfets) and an evaluate transistor, typically an nfet whose source is connected to the same pull-down network. Precharge occurs on one phase of the clock, a signal is input, and the evaluate occurs on the other phase of the clock. According to the standard rules of domino logic, an evaluate device is required for the first dynamic gate after a latch in order to ensure that the precharge completes successfully. To prevent a signal from propagating to the next domino stage, the output A of each stage has a static CMOS inverter or equivalent to perform a logic inversion that provides the intended causal evaluation of a cascade of many such stages.
Referring to the figures wherein like numerals refer to the same or similar elements throughout and in particular with reference to FIGS.
1
(
a
) and
1
(
b
), therein shown are simplified block diagrams of two possible configurations of a conventional domino circuit with the same logic function in which one critical path
150
feeds another critical path
160
. The circuit of FIG.
1
(
a
) is essentially the same circuit as FIG.
1
(
b
) except that the first gate after latch
118
may be a static gate
120
or a dynamic gate
140
. If it is a static gate
120
, as in FIG.
1
(
a
), the timing boundary or critical path starts on CLK
0
110
and ends on SINKA
122
. If the gate after latch
118
is a dynamic gate
140
, as shown in FIG.
1
(
b
), the timing boundary/critical path starts on CLK
0
110
and ends on SINKB
144
. The designer chooses based on the simulation modeling whether to make the first gate after latch
118
a static gate or a dynamic gate specifically to move the timing boundary between the two critical paths
150
,
160
. If the designer uses a static gate
120
, the designer adds the delay of that gate to the first critical path
150
; by using a dynamic gate
140
, the designer add the delay to the second critical path
160
.
FIG. 2
is a conventional dynamic delay inserted after latch
118
in FIG.
1
(
b
). The output SINKB
144
of latch
118
is input into dynamic gate
140
. Dynamic gate
140
comprises a precharge device, pfet P
10
, and an evaluate device, nfet N
10
. To prevent cascading onto the next stage, there is a domino inverter INV
10
. Similarly dynamic gate
126
has a precharge of pfet P
20
and an evaluate transistor N
20
. Inverters INV
10
and INV
20
are standard elements of domino circuits to buffer dynamic stages. Nfet networks
210
and
220
may perform a logical operation on the input signal SINKB
144
. The operation of these domino circuit delays is known in the art and will not be explained here.
If the desig

Affiliated with

Also associated with

Rating

Programmable timing boundary in dynamic circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable timing boundary in dynamic circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable timing boundary in dynamic circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3000508