Polyphase clock generation circuit

Details Polyphase clock generation circuit Polyphase clock generation circuit

1994-01-06

1995-09-26

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 28, 327259, 377121, H03K 19096

Patent

active

054537070

ABSTRACT:
A single-phase clock and an output signal of a second delay circuit are inputted to a first NAND gate and a first NOR gate. The output signal of the first NAND gate is inputted to a gate of a first PMOS transistor of a first clock driver. The output signal of the first NOR gate is inputted to a gate of a first NMOS transistor of the first clock driver. Meanwhile, an inverted clock outputted from an inverter and an output signal of a first delay circuit are inputted to a second NAND circuit and a second NOR circuit. The output signal of the second NAND gate is inputted to a gate of a second PMOS transistor of a second clock driver. The output signal of the second NOR gate is inputted to a gate of a second NMOS transistor of the second clock driver.

REFERENCES:
patent: 4394586 (1983-07-01), Morozumi
patent: 4816700 (1989-03-01), Imel
patent: 4877974 (1989-10-01), Kawai et al.
patent: 4929854 (1990-05-01), Iino et al.
patent: 5086236 (1992-02-01), Feemster
patent: 5111076 (1992-05-01), Tarng
European Search Report EP 94 10 0443, dated Oct. 11, 1994.

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