Half-swing line precharge method and apparatus
High speed latch/register
High speed latch/register
High speed low power data transfer scheme
High speed output enable path and method for an integrated...
High speed, low power CMOS logic gate
High voltage level translator
High-performance clock-powered logic
High-speed domino logic with improved cascode keeper
High-speed logic embodied differential dynamic CMOS true single
High-speed, state-preserving, race-reducing,...
Hold-time latch mechanism compatible with single-rail to...
Hot-clock adiabatic gate using multiple clock signals with diffe
Hybrid data and clock recharging techniques in domino logic...