Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-07-31
2007-07-31
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
Reexamination Certificate
active
11211799
ABSTRACT:
Structures and methods for pseudo-CMOS dynamic logic with delayed clocks are provided. A pseudo-CMOS dynamic logic circuit with delayed clocks includes a dynamic pseudo-nMOS logic gate and a dynamic pseudo-pMOS logic gate coupled thereto. The dynamic pseudo-nMOS logic gate includes a delayed enable clock transistor coupled to a source region of at least two input transistors. The dynamic pseudo-pMOS logic gate includes a delayed enable clock transistor coupled to a drain of at least two input transistors. None of the logic input devices are connected in series.
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Cho James H.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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