Circuit arrangement

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Details

C713S400000, C713S500000, C713S501000, C713S502000, C713S503000, C713S600000, C713S601000

Reexamination Certificate

active

07376856

ABSTRACT:
An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for receiving a pulse of a clock signal (CK) to introduce data thereinto and output said introduced data and a shift register (2), comprising the D flip-flops (F1to F7) for introducing the data thereinto in accordance with the pulse to output the introduced data, for processing the outputted data from the D flip-flop (F0), wherein the circuit device (1) comprises a control circuit (3) for controlling whether the D flip-flops (F1to F7) are supplied with the pulse of the clock signal (CK) on the basis of outputted data from the D flip-flop (F0) in accordance with the pulse of the clock signal (CK) and data to be introduced into the D flip-flop (F0) in accordance with the next pulse.

REFERENCES:
patent: 5670904 (1997-09-01), Moloney et al.
patent: 5742224 (1998-04-01), Gadducci et al.
patent: 5883529 (1999-03-01), Kumata et al.
patent: 6198415 (2001-03-01), Yoshikawa et al.
patent: 6629250 (2003-09-01), Kopser et al.
patent: 6630853 (2003-10-01), Hamada
patent: 6710637 (2004-03-01), Chan
patent: 6847239 (2005-01-01), Leifso et al.
patent: 0524712 (1993-01-01), None
patent: 0703663 (1996-03-01), None
patent: 0703663 (1996-03-01), None

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