Capture clock generator using master and slave delay locked...

Details Capture clock generator using master and slave delay locked... Capture clock generator using master and slave delay locked...

2005-01-04

2005-01-04

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

06839860

ABSTRACT:
A clock generator comprising a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.

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