Circuit interface synchronization using slave variable delay loo

Details Circuit interface synchronization using slave variable delay loo Circuit interface synchronization using slave variable delay loo

1997-12-10

1999-10-12

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

G06F 112

Patent

active

059648805

ABSTRACT:
A method and apparatus is provided for synchronizing clock signals. The method includes receiving a first reference clock signal, generating a second clock signal, modifying the second clock signal to synchronize a first feedback input clock signal with the first reference clock signal, and modifying the second clock signal to synchronize a second feedback input clock signal with a second reference clock signal. The apparatus includes a phase aligning device having a first reference clock input adapted to receive a first reference clock signal, a first feedback input, and an output. A fixed delay device is coupled between the output of the phase aligning device and the first feedback input of the phase aligning device. A slave loop is coupled to the output of the phase aligning device.

REFERENCES:
patent: 5101117 (1992-03-01), Johnson et al.
patent: 5552726 (1996-09-01), Wichman et al.
patent: 5570054 (1996-10-01), Takla
patent: 5644604 (1997-07-01), Larson
patent: 5815016 (1998-09-01), Erickson

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