Using field programmable gate array (FPGA) technology with a...
Using IMPDEP2 for system commands related to Java...
Using IMPDEP2 for system commands related to Java...
Using multiple decoders and a reorder queue to decode...
Using on-chip and off-chip look-up tables indexed by...
Using padded instructions in a block-oriented cache
Using register rename maps to facilitate precise exception...
Using temperature data for instruction thread direction
Using thread urgency in determining switch events in a...
Using two barrel shifters to implement shift, rotate, rotate...
Utilizing a program counter with one or more data counters...
Utilizing a scoreboard with multi-bit registers to indicate...
Utilizing an advanced load address table for memory...
Valid bit generation and tracking in a pipelined processor
Valid bit generation and tracking in a pipelined processor
Validating prediction for branches in a cluster via...
Variable 16 or 32 bit PCI interface which supports steering...
Variable address length compiler and processor improved in...
Variable byte-length instructions using state of function...
Variable cycle instruction execution in variable or maximum...