Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2008-07-02
2009-10-13
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S037000
Reexamination Certificate
active
07603540
ABSTRACT:
A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
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Doering Andreas C.
Dragone Silvio
Herkersdorf Andreas
Hofmann Richard G.
Kuhlmann Charles E.
Chan Eddie P
Fennema Robert E
International Business Machines - Corporation
McBurney Mark E.
Yee & Associates P.C.
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