Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
1998-06-30
2002-10-15
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Instruction fetching
Reexamination Certificate
active
06467037
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to executing instructions utilizing a program counter and a data counter. More specifically, the invention relates to executing virtual machine instructions utilizing a program counter with one or more data counters that refer to data values stored in a data section that are associated with virtual machine instructions specified by the program counter.
Instructions that are executed by computers often have a standard format: an operation code (opcode) followed by zero or more operands. The opcode specifies the operation that the computer is to perform and the optional operands specify data that are associated with the operation. For example, the opcode can instruct the computer to push a value on the stack and the operand can specify the data value to be pushed on the stack. The operands can specify data in a variety of forms including data values, addresses, and the like.
FIG. 1
shows a traditional instruction section including instructions for computer execution. An instruction section
101
includes multiple instructions for computer execution. An instruction
103
consists of an opcode
105
and no operands. As shown, an instruction
107
consists of an opcode
109
and an operand (e.g., data value)
111
. An instruction
113
consists of an opcode
115
and an operand
117
. Instructions can also include multiple operands (not shown).
Typically, all of the opcodes have the same length. However, it is common for the operands to be of varying lengths. For example, the opcodes shown in
FIG. 1
can be a single byte long. operand
111
can be a two-byte data value (e.g., 16-bit value) and operand
117
can be a four-byte data value (e.g., 32-bit value).
When a computer accesses data from memory, it is usually more efficient if the data is aligned. The alignment depends on the data size (e.g., an n-bit data value usually should be n-bit aligned). Generally, access is most efficient if the data is aligned on a word boundary. As an example, if a computer is able to access aligned 32-bit values in a single operation, there will be a significant performance increase if the 32-bit data values are aligned on word boundaries. The 32-bit data values that are not aligned can require multiple read operations and operations to assemble the component parts of the desired data value. For example, many reduced instruction set computing (RISC) computers cannot read data that is not aligned in one instruction, but must use several instructions.
There have been attempts to ensure that data values are aligned.
FIG. 2
shows an instruction and data section that has been utilized in Smalltalk
80
. An instruction section
151
includes opcodes and indices. The indices specify data values in a data section
153
. As shown, an opcode
155
is followed by an index
157
and index
157
specifies a data value
159
in data section
153
.
Accordingly, when an opcode requires a data value, the opcode is followed by an index that specifies a data value in a data section. Because the data values are stored together in a data section, the data section can be aligned so that the data values can be more efficiently read by the computer. Although this solution has been successful for some applications, disadvantages include that following the index (i.e., adding the index to a pointer) is an additional burden that can create slower run time performance and the size of the program is larger because of the space occupied by the indices.
Another solution has been to align data values within the instruction section.
FIG. 3
shows an instruction section where the data values are aligned. An instruction section
201
includes opcodes and any associated data values. When an opcode requires one or more data values, the data values are aligned following the opcode. For example, an opcode
203
requires two data values
205
and
207
. If the data location following opcode
203
is not aligned, a null space
209
is utilized so that data values
205
and
207
are aligned.
The contents of null space
209
is generally unimportant (although it is typically zeroed out) as when the computer is executing opcode
203
, the computer determines that the data location following the opcode is not aligned so the computer skips the null space and retrieves data values
205
and
207
at aligned data locations. Although t his solution has proved successful in some applications, the size of the program is increased due to the null spaces.
There is a need for innovative methods and systems that provide encoding schemes for instruction sets that allow both efficient decoding of the opcodes and fast access to operands of different sizes.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide methods and systems for utilizing a program counter with one or more data counters for executing instructions. The program counter specifies the opcode in the instruction section that is being executed by the computer. A data counter is utilized to specify a data location in a data section that can be associated with the opcode specified by the program counter. Accordingly, the data counter generally mirrors the movement of the program counter and allows the computer to easily access information stored in the data section. Several embodiments of the invention are described below.
In one embodiment, the invention provides a method of executing instructions. A program counter specifies an instruction in an instruction section for execution. Additionally, a data counter specifies a data location in a data section for use with the instruction. After the instruction specified by the program counter has been executed, the program counter can be incremented to a next instruction. The computer system can also determine if the data location specified by the data counter was for use with the instruction and if it was, the data counter can be incremented to a next data location.
In another embodiment, the invention provides a data structure stored by a computer readable medium for executing instructions. The computer readable medium stores an instruction section that includes multiple instructions and a data section that includes multiple data locations, each of the data locations being for use with one of the instructions. A program counter specifies an instruction in the instruction section and a data counter specifies a data location in the data section, where the data location can be use with the instructions specified by the program counter during execution.
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patent: 4086626 (1978-04-01), Chung et al.
patent: 4267581 (1981-05-01), Kobayashi et al.
patent: 4403310 (1983-09-01), Minami
patent: 4689738 (1987-08-01), Wijk et al.
patent: 5185873 (1993-02-01), Maejima et al.
patent: 5274775 (1993-12-01), Croson
patent: 6012138 (2000-01-01), Worrell
patent: 0 328 422 (1989-08-01), None
patent: 0897146 (1999-02-01), None
patent: 0917048 (1999-05-01), None
Beyer Weaver & Thomas LLP
Eng David Y.
Sun Microsystems Inc.
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