Electrical computers and digital processing systems: processing – Instruction alignment
Reexamination Certificate
1998-04-30
2001-01-16
An, Meng-Ai T. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction alignment
C712S206000, C712S207000, C712S213000
Reexamination Certificate
active
06175908
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to superscalar microprocessors and, more particularly, to the predecoding of variable byte-length computer instructions within high performance and high frequency superscalar microprocessors.
2. Description of the Relevant Art
Superscalar microprocessors are capable of attaining performance characteristics which surpass those of conventional scalar processors by performing concurrent execution of multiple instructions. Due to the widespread acceptance of the x86 family of microprocessors, efforts have been undertaken by microprocessor manufacturers to develop superscalar microprocessors which execute x86 instructions. Such superscalar microprocessors achieve relatively high performance characteristics while advantageously maintaining backwards compatibility with a vast amount of existing software developed for previous microprocessor generations such as the 8086, 80286, 80386, and 80486.
The x86 instruction set is relatively complex and is characterized by a plurality of variable byte-length instructions. An x86 instruction consists of from one to five optional prefix bytes, followed by an operation code (opcode) field, an optional addressing mode (Mod R/M) byte, an optional scale-index-base (SIB) byte, an optional displacement field, and an optional immediate data field.
The opcode field defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes. For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field follows the prefix bytes, if any, and may be one or two bytes in length. It is understood that when the opcode field is two bytes, the first byte thereof is considered a prefix. The addressing mode (MODRM) byte specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte is used only in 32-bit base-relative addressing using scale and index factors. A base field of the SIB byte specifies which register contains the base value for the address calculation, and an index field specifies which register contains the index value. A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is the optional displacement field, which may be from one to four bytes in length. The displacement field contains a constant used in address calculations. The optional immediate field, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
The complexity of the x86 instruction set poses difficulties in implementing high performance x86 compatible superscalar microprocessors. One difficulty arises from the fact that instructions must be aligned with respect to the parallel-coupled instruction decoders of such processors before proper decode can be effectuated. In contrast to most RISC instruction formats, since the x86 instruction set consists of variable byte-length instructions, the start bytes of successive instructions within a line are not necessarily equally spaced, and the number of instructions per line is not fixed. As a result, employment of simple, fixed-length shifting logic to align the instructions with the decoders cannot be achieved with x86 instructions.
Superscalar microprocessors have been proposed (but not published or otherwise made part of the prior art) that employ instruction predecoding techniques to help solve the problem of quickly aligning, decoding and executing a plurality of variable byte-length instructions in parallel. In one such superscalar microprocessor, when instructions are written within the instruction cache from an external main memory, a predecoder appends three predecode bits (e.g., a start bit, a functional bit and an end bit, referred to collectively as a predecode tag) to each byte. The start bit is set to one for the start byte of every instruction, and is zero otherwise. The end bit is set to one for the end byte of every instruction, and is zero otherwise. The functional bit is the predecode bit with a unique purpose. The functional bit associated with the end byte is set to zero for fast path instructions, and set to one for MROM instructions. The remaining functional bits from the start bit to the end bit (not including the end bit) are set according to whether the bytes are prefixes or not. In particular, all prefix bytes have their associated functional bit set to one and all non-prefix bytes have their functional bit set to zero for both fast path and MROM instructions.
As noted, the decode stage processes the prefix bytes to properly decode instructions. Predecoding instructions using the above identified proposed predecode tag encoding is advantageous in that the decode stage need not perform extra calculations to determine the location of the prefix bytes within an instruction since all the prefix bytes are identified with a set functional bit. Additionally, because the opcode byte follows the prefix bytes, if any, the decode stage need not perform extra calculations to identify the location of the opcode since the opcode is identified as the first byte with a cleared functional bit. Avoiding the extra step of identifying prefixes in an instruction reduces circuitry and delay within the decode stages. However, the above identified proposed predecode tag encoding presents a problem. Namely, it is impossible to determine whether an instruction is fast path or MROM until the end byte is scanned. This presents a problem for split line instructions in which the start byte of a particular is located in a first set of sixteen bytes while the end byte of the instruction is located in a subsequent set of sixteen bytes.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a superscalar microprocesor employing a predecode unit adapted for predecoding variable byte-length instructions in accordance with the present invention. In one embodiment, a predecode unit is provided which is capable of predecoding variable byte-length instructions prior to their storage within an instruction cache. The predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions to a plurality of decode units within the superscalar microprocessor. Additionally, one or more instruction decode stages within the superscalar microprocessor use the predecode tags in decoding the instructions prior to their execution.
In one implementation, the predecode unit generates three predecode bits associated with each byte of instruction code: a “start” bit, an “end” bit, and a “functional” bit. The start bit is set if the associated byte is the first byte of the instruction. The start bit is cleared otherwise. Similarly, the end bit is set if the associated byte is the last byte of the instruction. The end bit is cleared otherwise. The encoding of the functional bit is dependent on the start byte of the instruction. If the instruction is a fast path instruction, the functional bit associated with the start byte is cleared. If the instruction is MROM, the functional bit associated with the start byte is set. For bytes of an instruction other than the start byte, the encoding of the functional bit is dependent on whether the associated byte is a prefix or opcode. Namely, the functional bit is set when the associated byte is a prefix or opcode, and the functional bit is cleared when the associated byte is not a prefix or
Advanced Micro Devices , Inc.
An Meng-Ai T.
Conley, Rose, & Tayoun, PC
Merkel Lawrence J.
Patel Gautam R.
LandOfFree
Variable byte-length instructions using state of function... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable byte-length instructions using state of function..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable byte-length instructions using state of function... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554297