Variable cycle instruction execution in variable or maximum...

Electrical computers and digital processing systems: processing – Processing control – Mode switch or change

Reexamination Certificate

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C712S208000, C713S502000

Reexamination Certificate

active

07134003

ABSTRACT:
A data processing system2is provided which is responsive to program instructions that operate in a variable timing mode to require a variable number of processing cycles to complete. The system is also operable in a fixed timing mode, which may be programmable using a bit (or several bits) within a configuration controlling register, to operate in a fixed timing mode in which such instructions are forced to operate using a fixed number of processing cycles. Thus, suppression of instructions which fail their condition codes may be suppressed and early termination of program instructions similarly suppressed in a manner which helps resist an attack upon the security of the system by observing the number of processing cycles required to process certain data.

REFERENCES:
patent: 4566062 (1986-01-01), Ohnishi et al.
patent: 5802360 (1998-09-01), Fernando
patent: 5961633 (1999-10-01), Jaggar
patent: 59-5354 (1984-01-01), None
patent: WO 00/42499 (2000-07-01), None
patent: WO 01/69378 (2001-09-01), None

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