Variable address length compiler and processor improved in...

Details Variable address length compiler and processor improved in... Variable address length compiler and processor improved in...

2000-09-14

2010-11-23

Coulter, Kenneth R (Department: 2454)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C717S143000, C717S154000, C717S140000

Reissue Patent

active

RE041959

ABSTRACT:
The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

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